VLSI

VLSI Projects

projects for B.Tech students on VLSI. Abstract List
.
S. No Project Title Download Abstract
VLSI001 An Efficient Implementation of Floating Point Multiplier. Abstract
VLSI002 Design and Simulation of UART Serial Communication Module Based on VHDL. Abstract
VLSI003 Design of FPGA-Based Traffic Light Controller System. Abstract
VLSI004 32 Bit×32 Bit Multiprecision Razor-Based Dynamic Voltage Scaling Multiplier With Operands Scheduler. Abstract
VLSI005 A Parallel-Serial Decimal Multiplier Architecture. Abstract
VLSI006 Design and Implementation of Automated Wave-Pipelined Circuit using ASIC. Abstract
VLSI007 Design of Low Power TPG Using LP-LFSR. Abstract
VLSI008 Low-Power and Area-Efficient Carry Select Adder. Abstract
VLSI009 A High Speed Binary Floating Point Multiplier Using Dadda Algorithm Abstract
VLSI010 Design a DSP Operations using Vedic Mathematics. Abstract
VLSI011 Design High Speed Low Power Multiplier using Reversible logic. Abstract
VLSI012 Design High Speed Low Power Multiplier using Reversible logic a Vedic Mathematical Approach Abstract
VLSI013 Design of High Performance 64 bit MAC Unit. Abstract
VLSI014 High Performance Hardware Implementation of AES Using Minimal Resources. Abstract
VLSI015 Implementation and Comparison of Effective Area Efficient Architectures for CSLA. Abstract
VLSI016 Implementation of I2C Master Bus Controller on FPGA. Abstract
VLSI017 Low-Power, High-Throughput, and Low-Area Adaptive FIR Filter Based on Distributed Arithmetic Abstract
VLSI018 Novel High Speed Vedic Mathematics Multiplier using Compressors. Abstract
VLSI019 Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic. Abstract
VLSI020 An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator. Abstract
VLSI021 Area-Delay Efficient Binary Adders in QCA. Abstract
VLSI022 Bit-Level Optimization of Adder-Trees for Multiple Constant Multiplications for Efficient FIR Filter Implementation. Abstract
VLSI023 Design and Development of FPGA Based Low Power Pipelined 64-Bit RISE Processor with Double Precision Floating Point Unit. Abstract
VLSI024 Design of Efficient Binary Comparators in Quantum-Dot Cellular Automata. Abstract
VLSI025 High Speed Convolution and Deconvolution Algorithm Abstract
VLSI026 High-Throughput Multistandard Transform Core Supporting MPEGH.264VC-1 Using Common Sharing Distributed Arithmetic. Abstract
VLSI027 Implementation Of Floating Point Mac Using Residue Number System. Abstract
VLSI028 Verification of Four Port Router for NOC. Abstract
VLSI029 A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications Abstract
VLSI030 Design and Development of FPGA Based Low Power. Abstract
VLSI031 A Novel Area-Efficient VLSI Architecture for Recursion Computation in LTE Turbo Decoders Abstract
VLSI032 Efficient Coding Schemes for Fault-Tolerant.. Abstract
VLSI033 High Speed Fir Filter Designs Based On Booth Multipler. Abstract
VLSI034 Low-Power and Area-Efficient Shift Register Using Recursive Approach to the Design of a Parallel Self-Timed Adder.. Abstract
VLSI035 An Area- and Energy-Efficient FIFO Design Using Error-Reduced Data Compression and Near-Threshold Operation for Image/Video Applications. Abstract
VLSI036 An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter SynthesisAbstract
VLSI037 Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay. Abstract
VLSI038 Design of Improved Performance Voltage Controlled Ring Oscillator. Abstract
VLSI039 Critical-Path Analysis and Low-Complexity Implementation of the LMS Adaptive Algorithm. Abstract
VLSI040 Data Encoding Techniques for Reducing Energy. Abstract
VLSI041 Consumption in Network-on-Chip. Abstract
VLSI042 Efficient FPGA Implementation of Address Generator for WiMAX Deinterleaver.. Abstract
VLSI043 Efficient Parallel Architecture for Linear Feedback Shift Registers. Abstract
VLSI044 Efficient VLSI Architecture for Decimation-in-Time Fast Fourier Transform of Real-Valued Data. Abstract
VLSI045 Input Vector Monitoring Concurrent BIST Architecture Using SRAM Cells. Abstract
VLSI046 Low-cost and high-speed hardware implementation of contrast-preserving image dynamic range compression for full-HD video enhancement. Abstract
VLSI047 Low-Power and Area-Efficient Shift Register Using Pulsed Latches. Abstract
VLSI048 Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations.. Abstract
VLSI049 RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing. Abstract